1. Field of the Invention
The present invention relates to electronics. More specifically, the present invention relates to switches.
2. Description of the Related Art
Analog to digital converters are widely used for converting analog signals to corresponding digital signals for many electronic circuits. For example, a high resolution, high speed analog to digital converter (ADC) may find application in broadband communications, video circuits, radar, and electronic warfare applications. In the field of analog to digital conversion, there continue to be many driving goals, such as speed, increased number of bits (relating to dynamic range and spur-free operation), power consumption, and size. Two of the most critical specifications remain speed and dynamic range.
The fastest ADC architecture is called “flash” conversion. A flash ADC produces an N-bit digital output in one step using a comparator bank comprised of 2N−1 parallel comparators. This architecture, however, is limited in dynamic range to about 8 bits, since the number of comparators grows rapidly as the number of bits N becomes larger. The next fastest converter technique is a subranging pipelined architecture.
Subranging ADCs typically use a low resolution flash quantizer during a first stage or “coarse pass” to convert an analog input signal into the most significant bits (MSB) of its digital value. An analog version of the MSB word, generated by a digital analog converter (DAC), is then subtracted from the input signal at a summing node to produce a residue or residual signal. The residue signal is amplified by an amplifier, and subsequently digitized by one or more additional stages or “fine passes” to produce the least significant bits of the input signal. The digital words produced by each stage are then combined by digital error correcting circuitry to produce a digital output representing the original analog input signal.
In a subranging ADC, the summing node is perhaps the most critical node in the chain. This is because an error appearing at the summing node cannot be corrected by the error correction circuit and will therefore appear as an error in the digital output. The problem that must be overcome is that when the input sample and hold (S/H) circuit begins its next sample, the quantizer and DAC have not reached equilibrium, resulting in a large voltage swing at the summing node. This causes some of the internal stages of the following amplifier to go into saturation. Once this happens, the settling time of the amplifier is lengthened considerably and the speed of conversion is significantly degraded.
A switch is typically used to isolate the amplifier from the summing node during the period when the driving circuits have not reached equilibrium. This switch must switch and settle rapidly. It must also provide isolation when off and provide linear operation when on. Prior art implementations, however, either perturb the summing node by capacitively coupling charge or affect the settling time by switching input stages within the amplifier.
Hence, there is a need in the art for an improved switch offering faster speed and greater accuracy than prior art switches.